1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to a cap wafer for packaging circuit elements formed on a base wafer, a semiconductor chip having the same, and a fabrication method thereof.
2. Description of the Related Art
Generally, a semiconductor chip, which is used in various electronic products, such as, for example, televisions, personal data assistants, mobile phones, etc., receives electric power from the outside to carry out a specific operation. Also, since the semiconductor chip has delicate electronic circuits built therein, it can be easily damaged by external impacts.
Accordingly, in fabrication, the semiconductor chip essentially requires a packaging process, which electrically connects the electronic circuits therein to the outside and at the same time, hermetically packages them to withstand external impacts, thereby allowing the semiconductor chip to have a physical function and shape.
As an example of techniques used in the packaging process, a wafer level packaging technique, which bonds a cap wafer having a shape to a base wafer in which circuit elements are formed, are known. The wafer level packaging technique is used as a packaging technique to satisfy reduced weight, decreased size and enhanced performance requirements of the electronic products, and is actively researched and developed in the semiconductor and micro electro mechanical system (MEMS) technology areas.
However, due to a demand of reducing the electronic products in size according to the reduced weight, the decreased size and the enhanced performance thereof, the semiconductor chip fabricated using the wafer level packaging technique is designed so that penetrated electrodes formed in the cap wafer are maximally reduced in size. As a result, the penetrated electrodes are formed so that aspect ratios thereof are enlarged. If the aspect ratios of the penetrated electrodes come large, it is not easy to form straight-via holes for forming the penetrated electrodes during fabrication. Also, even though the straight-via holes are formed, it is difficult to deposit a seed layer on side surfaces of the straight-via holes, and to completely fill the straight-via holes with a conductive material due to a difference of plating speed between an upper surface of the cap wafer and the insides of the straight-via holes, and a difference of plating speed according to depths of the straight-via holes. As a result, gaps or voids may occur in the resultant penetrated electrodes. If the gaps occur, fine dusts may go into the semiconductor chip through the gaps. As a result, the chip may malfunction due to the dusts that came in through the gaps. Also, if the voids occur, impurities in the voids may be oxidized, and thereby the chip may malfunction or suffer damage in operation.
To address the above problems, as a method of reducing the semiconductor chip in size, a method of forming the penetrated electrodes in a cap wafer with a decreased thickness can be considered. In this case, however, there is a limit to how far the thickness of the cap wafer may be reduced. This is because, in order to increase productivity, a size of wafer for forming the cap wafer is gradually increasing. Thus, a thickness of wafer, which can be fabricated without resulting in a wafer damage in a chip fabrication, is restricted.
As another method of reducing the semiconductor chip in size, a method of joining a sufficiently thick cap wafer with a base wafer, thinning an upper surface of the cap wafer to reduce the thickness of the cap wafer and then forming the penetrated electrodes in the cap wafer, can be considered. In this case, the above problem that the wafer is damaged due to the decreased thickness in the chip fabrication may be addressed. However, a problem occurs in that circuit elements of the base wafer are often damaged in forming the penetrated electrodes. Also, the method does not simultaneously form the cap wafer and the base wafer, but should form the base wafer prior to forming the cap wafer. Accordingly, a problem occurs in that a chip fabrication time is lengthened.
Thus, it would be advantageous to have a new fabrication method of the semiconductor chip which does not generate the above problems, even though the penetrated electrodes are formed in a high aspect ratio or the thickness of the cap wafer is decreased to reduce the semiconductor chip in size.